SMIC Achieves Volume Production of 5nm-Class N+3 Node Without EUV Lithography
Semiconductor Manufacturing International Corporation (SMIC) has reached a significant milestone by commencing volume production of its latest 5nm-class process node, known as SMIC N+3. This achievement marks a new era for China’s semiconductor industry, as the N+3 node is now the most advanced chip manufacturing process in the country that does not rely on extreme ultraviolet (EUV) lithography. Instead, SMIC utilizes deep ultraviolet (DUV) lithography to fabricate its silicon wafers, demonstrating remarkable progress in domestic chipmaking capabilities.
Recent analysis by TechInsights has confirmed that Huawei’s Kirin 9030 system-on-chip (SoC) is manufactured using the SMIC N+3 node. This development brings China closer to semiconductor self-sufficiency, as it represents a full generation leap over the previous SMIC N+2 node, a 7nm-class process previously used for Huawei’s Ascend AI accelerators and other infrastructure components.
Technical Challenges of DUV-Based 5nm Production
While SMIC’s progress is impressive, manufacturing advanced nodes with DUV lithography presents significant technical hurdles. EUV lithography, with its 13.5nm wavelength, is the industry standard for producing leading-edge chips at 5nm and below. In contrast, DUV immersion scanners operate at a 193nm wavelength, making it much more challenging to achieve the fine features required for 5nm-class nodes.
To overcome these limitations, SMIC has implemented advanced multi-patterning techniques, likely including self-aligned quadruple patterning (SAQP), to push the capabilities of DUV lithography. According to TechInsights, SMIC’s N+3 node achieves metal pitches close to 35nm in a single print, but requires multiple patterning rounds to fully realize the design. These complex processes, while effective, introduce significant yield challenges. The aggressive scaling of metal layers increases the likelihood of defects, resulting in a higher proportion of discarded or downgraded chips. As a result, the production of the Kirin 9030 SoC on the N+3 node is likely operating at a financial loss due to these yield constraints.
The techniques used by SMIC are refinements of established DUV processes that have been studied and applied in the semiconductor industry for decades. However, the yield rates for the N+3 node remain uncertain, and available information suggests that overcoming these challenges will require further innovation and optimization.
Domestic Equipment Development and Industry Implications
In a parallel effort to reduce reliance on foreign technology, SMIC has been testing an immersion DUV lithography scanner developed by Shanghai Yuliangsheng Technology. This domestically produced equipment is designed for 28nm-class processes and is comparable to older lithography systems such as the ASML Twinscan series from 2008. While this represents a step forward for China’s local wafer fabrication equipment industry, it is unlikely that such tools have been used for the advanced N+3 node in such a short timeframe.
Most industry experts believe that SMIC’s N+3 node production still relies on DUV lithography equipment supplied by ASML, the leading global provider of advanced lithography tools. The development of domestic alternatives remains in its early stages, but ongoing investments and research signal a strong commitment to achieving greater technological independence in the future.
SMIC’s successful ramp-up of the N+3 node underscores both the progress and the challenges facing China’s semiconductor sector. While the use of DUV lithography for 5nm-class production is a technical feat, yield and cost issues remain significant obstacles. Nevertheless, this achievement highlights the determination and expertise driving innovation in China’s chip manufacturing industry.
